You can use the GT wizard to generate
the settings for customization to be manually
migrated into the source code wrapper
of the hard-IP block. The wizard has two
protocol templates to support the PCI
Express physical layer: PCI Express Gen1
and PCI Express Gen2.
Serial RapidIO
Like PCI Express, the Serial RapidIO protocol
is also defined in three layers, in this
case, physical, logical and transport. It is the
nature of this industry to leverage as much
of existing technical specifications as is relevant
for the purpose of the protocol. Thus,
Serial RapidIO’s physical layer uses the
XAUI electrical interface (IEEE 802.3ae-
2002, Clause 47) as a guide in defining its
own parameters for the AC electrical specification.
Since RapidIO and XAUI have
similar applications goals, Serial RapidIO
designers were able to reuse their existing
XAUI electrical designs. The GT wizard
supports the Serial RapidIO PHY by means
of the Serial RapidIO template.
Triple-Rate SDI Video
Triple-rate SDI video reference designs are
based upon the Society of Motion Picture
and Television Engineers (SMPTE) standards.
Our integrated reference design supports
several standard- and high-definition
flavors of this standard, namely SD-SDI,
HD-SDI, Dual Link HD-SDI and 3G-SDI.
The physical connection to the High-
Speed Serial Transceiver is differential
CML driving an external cable driver (for
transmit) or an external adaptive receiver
equalizer. The common serialization protocol
between the standards is very specific
and is designed in the FPGA fabric. This
protocol has long runs of 1’s and 0’s that
require very large AC coupling capacitors.
Broadcast equipment is networked
together with the Triple-Rate SDI standards
running over 75-ohm coaxial cables. The
GT wizard supports SD/HD/3G-SDI reference
designs using the HD-SDI protocol
with the template of that name. The trimode
reference design uses the dynamicreconfiguration
port to reconfigure the
gigabit transceiver to support the SD and
3G trimodes. In these modes, SD-SDI and
3G-SDI use the phase-locked loop inside
the GT to recover the data at 2.97 Gbits/s.
Xilinx Trimode Ethernet
The Trimode Ethernet MAC is a Xilinx
implementation of the 10/100/1G Ethernet
protocol. Xilinx offers the TEMAC
LogiCORE (soft IP) and Trimode Ethernet
Wrapper for Integrated Block (hard IP). For
the soft IP, the 1000BASE-X PCS/PMA or
SGMII LogiCORE can connect seamlessly.
SGMII is a serial connectivity standard that
supports 10/100/1G operation.
The connection between the TEMAC
and the GTX is always 1 Gbit/s, but the
interface will sample less frequently for
the slower rates. The SGMII option is
different in the wizard’s PCS and PMA
settings, and is available as a separate
protocol template.
Applications using copper wires
(1000BASE-T) do not have the same division
of logic between the FPGA and the
1000BASE-T PHY as in a 1000BASE-X
(“X” signifies optical) PMD device. In the
case of a 1000BASE-T device, the PCS, the
PHY device generally implements the PMA
and PMD PHY sublayers. The designer can
implement the MAC in the FPGA and the
GT through a GMII interface; the MAC
does not to implement any of the PHY
layer. Thus, there is no GT wizard protocol
template for 1000BASE-T.
The TEMAC wrapper is an HDL wrapper
around the hard TEMAC sub-block and
the GT I/O blocks (1000BASE-X/SGMII
is integrated into the hard TEMAC
already). The Ethernet LogiCORE documentation
supplies implementation details.
The GT wizard supports the Tri-Mode
Ethernet protocol using the GigE
(SGMII/1000Base-X) template.
In conclusion, industry-standard protocols
are constantly changing, and it seems
one or two new ones emerge every year. As
such, the terminology and underlying technologies
can be as confusing as tax law. The
more you understand about the details of a
given protocol’s physical-layer scheme, the
easier it will be to determine the best highspeed
serial transceiver wizard protocol template
to use as a starting point for your
design projects.
XPLANATION:FPGA101
Third Quarter 2009 Xcell Journal 47
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