XPLANATION:FPGA101
For example, interfacing to a memory
(DDR2, QDR, RLDRAM, etc.), may
require termination inside the FPGA for signal
integrity, but it will typically consume
more power and raise junction temperature.
Meanwhile, if you are interfacing an
FPGA to an ASIC/ASSP, you must select
the interface based on what the ASIC/ASSP
target specifies (LVDS, HSTL, etc.). And if
you are interfacing one FPGA to another
FPGA, you may choose the interface based
on the design’s performance needs and may
be able to more readily find opportunities
for power optimization.
While both inputs and output consume
power, the reference standards like LVDS,
HSTL and SSTL consume the most. For
outputs, the higher-drive-strength standards
consume the most power and the power
varies linearly with output enable rates and
toggle rates. However, LVDS is an exception
in that it is based on a fixed current source,
which is independent of toggle rate.
For inputs, the referenced standards
consume a lot of power because their
receive structure incorporates a differential
receiver and also because they include a
selectable internal termination. Both consume
DC power.
A feature called T_DCI (dynamically
three-statable digitally controlled imped-
Intermediate logic propagation glitches cannot pass a flip-flop.
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Glitches propagate and multiply the more logic levels they travel.
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Glitch energy reduced by adding more "roadblocks."
Figure 10 – Glitch propagation and blocking with inserted flip-flops
ance) in the Virtex-5 allows the user to
dynamically remove the termination
when a given I/O pad is used as an output.
This is useful for the data bus or
memory interface, and depending on the
read vs. write ratio, it can rein in a fair
amount of power (see Figure 4).
When selecting I/O interfaces, wise
choices that balance performance and
power are important. You should use interfaces
like LVDS when your design needs
absolute maximum performance and minimum
noise or the target device requires the
I/O standard.
Because termination generally consumes
a large amount of power, you need
to use it wisely and take into account the
balance of power and performance.
Schemes that use external termination or
no termination can greatly reduce power.
Yesterday, Today and Tomorrow
Ever since power management began to
loom as a big issue, Xilinx has been diligently
building power-optimization technologies
into tools throughout our ISE
suite. For example, in addition to launching
XPE and XPower Analyzer, a few years ago
we gave ISE a power-optimized router that
works based on known capacitance of routing
resources inside the FPGA.
42 Xcell Journal First Quarter 2009
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Also, you can configure ISE’s poweroptimized
synthesis engine to automatically
locate small arrays in the source code and
synthesize them into LUTRAM. At your
command, the engine will locate large
arrays (in a size you specify) and synthesize
them into block RAM. If it finds a large
counter, it can implement it in a DSP48
block. It can also make smart choices when
replicating logic to ensure it implements
only the optimal amount.
More recently, Xilinx has introduced an
optimized placer that will group functions
together to minimize routing distance and,
hence, capacitance. A related set of tools
called PlanAhead™ allows you to take
hierarchical groups of logic and physically
place them in rough areas inside the FPGA.
This helps reduce capacitance and speed up
routing time as well.
As Xilinx continues to pioneer technology
on the latest process nodes, we anticipate
that dynamic and static power will
continue to pose challenges. But at the
same time, we are diligently working not
only to optimize our tools and methods for
power management, but also to make a
concerted effort to nip power problems in
the bud—in silicon.
For more information on Xilinx power
management, visit www.xilinx.com/power.
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