Reference Design Functionality Description
DVI Pass-Through • Capture a video stream input port
• Perform real-time image processing on the video stream
• Display the processed video
DVI Frame Buffer • Capture a video stream from a camera
• Perform processing on the video stream
• Buffer the video stream in external memory
• Report memory bandwidth utilization data
Camera Frame Buffer • Capture a video stream from a camera
• Perform processing on the video stream
• Buffer the video stream in external memory
• Display the processed video at a different rate
• Use a MicroBlaze to configure the video pipeline
Video Processing • Capture video stream from an S-video interface
• Support weave and de-weave access to video memory
• Perform gamma processing and 2D FIR filtering
Hardware Co-SIM • Initialize a point-to-point connection to the platform
• Any design within System Generator can add a HW-CoSIM token
• Validation acceleration with hardware in-the-loop
Processor
System Reset
Clock
Generator
Camera
In
Key:
Camera
In
EDK IP
VSK IP
Table 1 – Reference designs
Block
RAM
ILMB DLMB
MicroBlaze
Processor
Camera
Processing
Gamma
MDM
IXCL
DXCL
PLB
VIDEO
_TO_
VFBC
V
F
B
C
UART
MPMC
Figure 1 - Camera reference design
First Quarter 2009 Xcell Journal 19
V
F
B
C
GPIO
DIP Switches
System ACE
XCELLENCE IN AUTOMOTIVE & ISM
Video Starter Kit Version 2.0
The latest version of the XtremeDSP
Video Starter Kit (VSK) for the Spartan-
3A provides a comprehensive platform
that accelerates the development of video
applications on Xilinx FPGAs. Designed
to leverage the cost/performance advantages
of the Spartan-3A DSP FPGA device
family, the kit offers an updated set of
video reference designs based on an
embedded design framework that allows
customers to focus on their unique valueadded
development.
The VSK provides multiple reference
designs that can accelerate the development
of video applications running on
Xilinx FPGAs. Each reference design is
built upon a common framework and uses
multiple interfaces for the I/O of video
data to the FPGA. Table 1 lists each reference
design and the video processing and
connectivity capability it illustrates.
GPIO
Push Buttons
XPS IIC
Display
Controller DVI_OUT DVI_OUT
GPIO
LEDs
XPS IIC
PLB
ARB
To view a Ceros magazine you need to have JavaScript enabled in your browser and have the flash player 8 or higher installed. To install the latest flash player, click the icon above, install the flash plugin and then click here to refresh this page.