Quad
2 x 5.15G to 10G Mux
Saves PCB Space
10
1
2
3
instantiate or implement an NPU architecture
on the fly that is best suited to read the
data, even run a security check in it, negotiate
the fastest route to its destination and
then forward the data there.
“FPGAs have traditionally performed
embedded RISC and control plane functions,”
said Loring Wirbel, longtime communications
watcher and moderator of EDN
Magazine’s new FPGA Gurus Web site.
“Today’s FPGAs can now handle a lot of
datapath functions, so now seemingly a single
FPGA—depending on how it’s partitioned—can
serve as an aggregation box in an
enterprise or one of the blades in a big switching
center. So you don’t need coprocessing if
you have partitioned things correctly. One of
the stories of the death of the network processor
is that slowly but surely, FPGAs started
taking over the NPU’s function.”
Wirbel notes that traditionally, as each
new generation of equipment has rolled
out, there is a very brief opportunity for
NPU vendors to field specialized packetforwarding
engines. But in the wink of an
eye the opportunity passes, he said, and the
engines get replaced with FPGAs.
“As we start moving to 40G and 100G
networks, there will be a temporary place for
very fast engines that just do the packet forwarding,
just as there was for 1G and 10G
[technology],” Wirbel said. “But the thing
is, as you move to the new feature sizes, that
is only going to be a narrow window and
they may very likely just skip looking over
10x "MLD" = 20 x 5.15G
SFP ± 10g Phy
SFP ± 10g Phy
SFP ± 10g Phy
SFP ± 10g Phy
2
2
2
2
Figure 2 – Sarance Technologies’ 100GE MAC solution implemented with Virtex-5 FPGAs
100G
MAC
TM &
PP @
100G
System
MAC
the ASSPs and go directly with an FPGA.
Every generation has had that brief window
where they use ASSPs, but with each generation
that window is becoming more narrow—eventually
it will stay closed.”
Advancing FPGA Technologies for Wired Comms
Today, Xilinx’s largest Virtex-5 TXT
XC5VTX240T device contains 37,440
logic slices with a total of 239,616 logic
cells. This architecture has afforded design
teams and IP vendors great opportunities
to innovate solutions that support XAUI,
RXAUI, Interlaken, Sonet, ODN and
many other wired standards with the most
advanced FPGA silicon to date.
For example, Xilinx worked closely with
Sarance Technologies to provide the industry’s
first 100GE media-access controller, a
full-featured, IEEE 802.3ba-compliant
solution implemented with Virtex-5
FPGAs (Figure 2).
Sarance announced in mid-2008 that its
100GE MAC solution was up and running
on tier-one vendor hardware prototypes
using two Virtex-5 FXT FPGAs, 10 external
10-Gbps physical-layer devices and a
variety of system-side interfaces.
The 100GE MAC-to-Interlaken bridge
solution that the new Virtex-5 TXT FPGA
platform supports is a low-risk way to condense
functionality into a single FPGA
and three external quad serdes muxes. In
this implementation, Xilinx’s 64/66 and
64/67 encode/decode gearboxes are built
First Quarter 2009 Xcell Journal 13
20-40 SERDES
Interlaken or XAUI or
RXAUI or
Customer
Proprietary
into the GTX transceiver, saving nearly
one-fifth of the logic count and power
consumption of the design.
In June 2008, telecommunications
giant Comcast Corp. announced it had
successfully completed a 100GE technology
test over its existing backbone infrastructure
between Philadelphia and
McLean, Va., using the industry’s first
100GE router interface. The system used
the same Sarance Technologies’ High Speed
Ethernet IP Core (HSEC) running on a
Virtex-5 FXT FPGA that is supported by
the Virtex-5 TXT platform today.
The demonstrations follow up on early
achievements in the 100GE domain. In
November 2006, Xilinx FPGAs were the
vehicle used to showcase the world’s first
successful 100GE transmission through a
live production network demonstrated at
the SC06 International Conference, the
confab of high-performance computing,
networking, storage and analysis.
Finisar teamed with Level 3
Communications, Internet2 and the
University of California at Santa Cruz to
demonstrate the transmission of 100GE
traffic over Level 3’s DWDM network
from the show site in Tampa, Fla., to
Houston and back—a total of 4,000 miles.
The Xilinx FPGA electrically transmitted
all ten signals to ten 10-Gbps XFP optical
transceivers, which converted the signals into
the optical domain. From there, the signals
traveled to Infinera’s commercially available
DTN Switched WDM System, which handed
them off to the Level 3 network.
Overall, FPGA technologies are
advancing fast. With each turn of Moore’s
Law, FPGAs offer communications
designers the ability to create higher-bandwidth,
next-generation networks. In the
not-so-distant future, network designers
will give FPGAs a more-central place in
their designs. How big that role turns out
to be will depend not only on the silicon,
but on the IP and hardware and software
tools customers have at their disposal.
Xilinx remains committed to creating
innovations for the wired communications
market, with an aim not just to maintain
its leadership but to build on it with new
programmable solutions.
COVER STORY
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