Xcell journal
PUBLISHER Mike Santarini
mike.santarini@xilinx.com
408-626-5981
EDITOR Jacqueline Damian
ART DIRECTOR Scott Blair
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INTERNATIONAL Melissa Zhang, Asia Pacific
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Xilinx, Inc.
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© 2009 Xilinx, Inc. All rights reserved. XILINX,
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herein are trademarks of Xilinx, Inc. All other trademarks
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The articles, information, and other materials included
in this issue are provided solely for the convenience of
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L E T T E R F R O M T H E P U B L I S H E R
Customer Collaboration, Teamwork
Key to Next-Gen FPGA Development
Years of hard work and coordinated effort underlie a new Xilinx architecture.
Even before it’s launched, plans are under way for the next one.
At the year-and-a-half mark, I’ve been here at Xilinx long enough to have witnessed firsthand
the remarkable effort the company and its network of partners undertake to conceive
and design a next-generation FPGA, and the invaluable role you, our customers,
play in its creation. The many steps involved in developing one FPGA in pace with Moore’s Law
is remarkable. Doing two FPGAs at once, as Xilinx did this year, and then creating the Targeted
Design Platform strategy to automate customer flows is extraordinary.
Many years before the latest FPGA ends up on your desk, a small army of Xilinx product
development experts visit a selection of customers, potential customers and even former customers
to understand the requirements of their next-generation systems, what functionality they
plan to include and, in the case of the ex-customers, why they switched to an alternate approach
or device. We then vet the findings against the ongoing feedback gathered by Xilinx FAEs and
sales personnel.
Performing this due diligence with customers across multiple markets provides a basis for
making informed decisions about what functions to hardwire into next-generation FPGAs, what
soft IP to offer (or which IP partners to work with) and what design tool functionality designers
will need. Of course, this undertaking is tempered by the fact that to be successful commercially,
an FPGA architecture’s feature set must serve the needs of either a broad set of customers
or of those playing in high growth markets—or both.
While the customer interviews are under way, the financial and manufacturing teams are
doing their own extensive analysis of independent vertical-market and economic data as well as
foundry and process node capabilities. Collating all this research, the development experts and
silicon architects then start to formulate an architecture and associated tool and IP requirement
specifications. A big part of the architectural-specification process is evaluating which of the
many new, patented technologies our engineers have concocted to incorporate. So rich are the
choices that the biggest challenge by far is determining what not to include.
Indeed, often a given circuit or architecture could be really cool from a hardware-engineering
or academic standpoint. However, if the software can’t take advantage of it, or if the new circuitry
is too complicated for a broad set of users and including it would severely jeopardize a release
window, then from a business perspective, it’s wise to omit it.
After several cycles of refinement, including reviews with Xilinx’s Customer Advisory Board
and Field Advisory Board, we finalize the overall architecture specification and the chip architects
and designers kick off their intensive design work. Simultaneously, the tool development
group begins to assess what tools will be needed to support the size of the new architecture and
any new circuitry the FPGA incorporates; the IP group transitions legacy intellectual property
and develops (or partners for) new IP; and the development board group starts formulating the
base and market-specific boards. With the advent of the Targeted Design Platforms, these groups
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