XCELLENCE IN WIRELESS COMMS
Implementing Wireless LAN
Interface in an FPGA
Complex, high-speed IP such as WLAN can run at full speed and even pass
Wi-Fi certification when built on the platform of a Xilinx device.
by Agnès Faïn
Senior Design Engineer
Wipro-NewLogic
agnes.fain@wipro.com
Wolfgang Meryk
Senior Product Marketing Manager
Wipro-NewLogic
wolfgang.meryk@wipro.com
Every company designing a complex and
high-speed intellectual-property (IP) core
like an IEEE 802.11 wireless LAN controller
faces the challenge of how to prove
the design is working and is of high quality.
A test chip is important, since only it
can show that the IP is silicon-proven. But
a test chip can capture the hardware design
state at only one point in time. However,
IP needs to be flexible to support a variety
of configurations and applications. WLAN
brings an additional requirement for flexibility
and upgradability, since there are still
new additions to market-relevant specifications
(Wi-Fi, ETSI/FCC) coming, and
some of them require or at least benefit
from hardware changes.
At Wipro-NewLogic, we decided to
investigate an FPGA-based platform to
solve this problem. We called the resulting
product the WiLDSYS board, to reflect the
name of our WLAN IP: WiLD a/b/g.
We formulated several key requirements
for this design. First, it had to support
running the WLAN IP at full speed
(54-Mbit/second air data rate for 802.11a
and 802.11g). Next, we needed a single
database for targeting both FPGA and
ASIC. Third, we wanted a very high level
of confidence that test results and bug fixes
from the FPGA target could be applied to
the ASIC target. Finally, we needed to
implement the external interfaces to the
host and to the radio all on the FPGA, so
as to minimize the number of external
components and to leverage the programmability
of the FPGA to allow alternative
interfaces in the future. During the course
of the project we found that the FPGA
platform not only met all these goals, but
even allowed us to take the WiLDSYS
board to a full Wi-Fi certification.
But let’s start at the beginning, with an
overview of the WiLDSYS design and the
selection of the FPGA device.
WiLDSYS Overview
Figure 1 shows the block diagram of the
WiLDSYS platform as we implemented it in
the original design. The WiLD Core to the
left comprises the 802.11 a/b/g media-access
controller (MAC) and modem hardware.
The MAC functions are split over the
WiLD Burst Processor, a buffer management
unit/DMA engine and the WiLD
Stream Processor, which takes care of the
RC4 and AES encryption. Both blocks serve
as master on the central Advanced High-
Performance Bus (AHB) and are not timing-critical.
The WiLD modem contains the
CCK/DSSS and OFDM signal processing
for the 802.11 a/b/g standard. Signal processing
designed for an ASIC is not easy to
map to an FPGA, and we will describe the
challenges and solutions in more detail later.
There is also a complete ARM7-based
processor platform that runs the Layer 2
MAC software. We support both access
point and station mode in the software.
34 Xcell Journal Fourth Quarter 2009
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